What is Open Source Silicon Root of Trust?

A silicon root of trust (RoT) is a foundational hardware security component embedded directly in a chip (at the silicon level).

It acts as the immutable, tamper-resistant anchor for a device’s security, verifying that the system boots into a known-good state, securely storing cryptographic keys, mediating access to firmware, and enabling features like secure boot, attestation, and encryption.

Unlike software-based security (which can be bypassed), a silicon RoT is part of the hardware itself, making it much harder for attackers to compromise.

An open source silicon root of trust takes this concept further by making the entire design hardware description (RTL), verification code, firmware, documentation, and integration guidelines publicly available under an open license.

This allows community auditing, independent verification, contributions from anyone, and avoids reliance on proprietary black-box implementations from a single vendor. The transparency reduces hidden vulnerabilities, builds broader trust, and accelerates adoption across industries (e.g., data centers, IoT, storage, peripherals, and consumer devices).

The Leading Project: OpenTitan

The primary and most prominent example is OpenTitan, explicitly described as the first open source project building a transparent, high-quality reference design and integration guidelines for silicon root of trust (RoT) chips.

• • Hosted by: lowRISC (a not-for-profit organization focused on open-source silicon).
  • Origins: Started in 2018 (inspired by Google’s internal Titan security chip), developed collaboratively with partners including Google, Nuvoton, ETH Zurich, G+D Mobile Security, Rivos, Seagate, Western Digital, Winbond, and others.
  • Goals: Create a high-quality, certifiable, vendor- and platform-agnostic RoT that is logically secure, auditable, and ready for real-world integration. It produces open IP that can be used as a standalone chip or embedded in larger SoCs.

Key technical highlights

• • Based on RISC-V (open-source instruction set architecture).
  • Available in discrete (e.g., “Earl Grey” top-level design) and integratable (e.g., “Darjeeling”) variants.
  • Includes a full security toolkit: key manager, entropy source, AES/SHA-2/HMAC accelerators, secure boot mediation, and more.
  • Actively supports post-quantum cryptography (PQC) for future-proofing against quantum attacks.
  • Permissively licensed (Apache 2.0) with complete RTL, design verification (DV), firmware, and documentation.

Current status (as of early 2026)

OpenTitan has reached production. Fabrication of commercial silicon began with Nuvoton in 2025, and it is now shipping in volume devices — including select Chromebooks (with datacenter integrations following). It is the world’s first open-source security chip in commercial products and the first commercially available open-source RoT supporting SLH-DSA-based secure boot for PQC.

Proprietary silicon RoTs (common in many chips and servers, e.g., from HPE or others) are effective but opaque — you must trust the vendor completely. OpenTitan’s open-source model enables security through transparency: the community can inspect, test, and improve the design, lowering costs, reducing vendor lock-in, and fostering innovation. It is designed for certification in cloud and IoT security use cases.

Another notable initiative is Caliptra (an open-source RoT specification from AMD, Google, Microsoft, NVIDIA, and others under the CHIPS Alliance), focused more on integrated RoTs for datacenter/confidential computing. However, OpenTitan remains the flagship full open-source silicon RoT project with working silicon in products.

In short, open-source silicon root of trust (exemplified by OpenTitan) represents a shift toward transparent, community-driven hardware security — making the most critical foundation of device trust auditable and accessible to all. You can explore it at opentitan.org or the GitHub repo for the full design.